01Core product
A reusable hardware-security block that generates, recovers, and diversifies cryptographic roots from one physics-based entropy source.
Who integrates it? Chip designers license this circuit-design IP and embed it inside their own MCU, SoC or ASIC. It is a design block for a custom chip.
02Core product
SASP combines Dynamic PUF with standardized cryptographic functions and lifecycle control to form a complete, configurable hardware root of trust.
Who integrates it? Semiconductor companies and OEM design teams license and configure this platform IP for their own secure MCU, SoC or ASIC.
Physics-based identity, root-key generation and recovery, checkpoint management, and true-random entropy.
AES, ECC, SHA, HMAC, SP 800-90A DRBG, SP 800-90B entropy, and post-quantum algorithm options.
PQC support varies by configuration. Ask about availability ↗
Key management, domain isolation, secure boot, firmware authentication and update, provisioning, lifecycle, and zeroization.
Available hardware
Physical implementations let teams start software and architecture work without waiting for a custom ASIC program.
Confirm current availability, certification scope and PQC algorithms for your chosen hardware and firmware configuration.
A production secure IC for embedded Dynamic PUF integration through standard host interfaces.
For embedded-device manufacturers: connect this physical chip to the host processor on your product’s circuit board.
A compact security anchor for adding PUF-backed identity, keys, and trusted operations to an existing system.
For OEMs and system integrators: add the module to a gateway, IoT device or industrial system through its host interfaces.
A programmable hardware security key for passwordless access, trusted identity, and cryptographic operations.
For enterprise IT and software teams: connect the USB key to a computer or compatible host for secure access and signing workflows.
A working platform for architecture validation, customer-specific proof of concept, and early software development.
For chip-design and embedded-software teams: evaluate the architecture on FPGA before integrating IP into custom silicon.
FPGA board reference: HuMANDATA Ltd., Japan.
From evaluation to integration
The platform is both a usable reference implementation and the foundation for customer-specific silicon.
01Prototype and refine the security architecture on the SASP FPGA reference platform.
02Validate functions and host integration on the FPGA reference platform. A dedicated SASP secure IC is in development; discuss availability and qualification needs with IIST.
03Select individual IP blocks or integrate a complete root-of-trust architecture into customer silicon.
Start a conversation
Tell us what you are securing. We will map the right path from evaluation hardware to customized silicon IP.